Showing posts with label Computer Architecture. Show all posts
Showing posts with label Computer Architecture. Show all posts

Control Unit | CSO

Computer Architecture , CSO
Control Unit | CSO

Control Unit


There are two type of control organisation:
  1. Hardwired control
  2. Micro Programmed control

Hard wired control


In hardwired organization the control logic is implemented with gates,Flip-Flops, Decoders, and other digital circuits.In this type we can optimize to produce fast mode operation.In hardwired control we can change the wiring among component if needed.

Micro Programmed control


In micro programmed organization the control information is stored in a control memory.The control memory is programmed to initiate the required sequence of micro operations.In micro programmed control any modification is done by updating micro program in control memory.
In the above diagram we have two decoders, a sequence counter,number of control logic gates.Here an instruction is read from memory is placed in (IR). The operation code in IR i.e bit 12 through 14 are decoded with a 3X8 decoder. The 8 output of decoder is D0 to D7.
Bit 15 of IR is transferred to a flip flop designated by symbol I.
Bit 0 to 11 are applied to the control logic gates.
The 4-bit sequence counter can count in binary from 0-15.The output of the counter are decoded into 16 timing single T0-T15.
The sequence counter(SC) can be incremented or cleared. synchronously.Most of the timing signals out of the 4 X 16 decoder.
Once the counter is cleared to 0 causing the next active time signal to be T0.

Instructions

There are basically three instruction format such as

1. Memory-Reference Instruction


Range of opcode=(000 to 110)
I=0 - Direct addressing mode
I=1 - Indirect addressing mode.

2. Register-Reference Instruction

opcode=111 , I=0
Here memory operand is not needed.
Operation is perform with AC register.

2. Input-Output Instruction


opcode=111 , I=1
Memory operand is not needed
Operation is performed with AC register.

Timing and Control


The timing for all register in the basic computer is controlled by a master clock generator.The CLK pluses are applied to all flip flop and registers in the system.The clock pulse do not change the state of register unless register is enabled by control signal. The control signal are generated in the control unit and provide control unit for the multiplexer in the common bus.


Content is Reference form Compute System Architecture, MORRIS M. MANO

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Addressing Modes | CSO

Computer Architecture , CSO
Addressing Modes | CSO

Addressing Modes


The Instruction format consist of 3-bit(12-14) operation code, a 12-address (0-11) and an indirect address mode bit designated by I.
    If
  • I=0 -> Direct Addressing Mode
  • I=1 -> Indirect Addressing Mode

Direct Addressing Mode


According to above diagram direct address is placed in address 22 in memory.Here I=0 so instruction is recognize as direct address instruction and the address part is the binary equivalent of 457.The control finds the operand in memory at address 457 and add it to content of AC (Accumulator)

Indirect Addressing Mode


According to above diagram Indirect address is placed in address 35 in memory.
Here I=1 , So instruction is recognize as indirect address instruction. The address part is binary equivalent of 300.
The control goes to address of operand.The address of operand in this case is 1350.The operand found in address 1350 is than added to the content of AC (Accumulator)
In Indirect address instruction need two references to memory to fetch an operand. The first reference is needed to read the address of the operand and the second is for the operand itself.

Effective Address


It is an address of an operand or target address such as 1350 is effective address in indirect address and 457 is effective address in direct address.


Content is Reference form Compute System Architecture, MORRIS M. MANO

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Introduction of Computer Organization | CSO

Computer Architecture , CSO
Introduction of Computer Organization | CSO

Computer Organization


The organization of the computer is defined by its internal registers, the timing and control structure and the set of instruction that it uses.The internal organization of a digital system is defined by the sequence of micro operations it performs on data stored in its registers.
The general purpose digital computer is capable of executing various micro operations and in addition can be instructed as to what specific sequence of operations it must perform. The user of a computer can control the process by mean of a program.
A program is a set of instructions that specify the operations,operands and the sequence by which processing has to occur.
A computer instruction is a binary code that specify a sequence of micro operations for computer.
Instruction code with data are stored in memory.The computer read each instruction from memory and place it in control register.

Instruction Code


An instruction code is a group of bits that instruct the computer to perform a specific operation.

Operation Code (Opcode)


It is a part of instruction code.The operation code of an instruction is a group of bits that define such operation as add, subtract, multiply, shift and complement.
The number of bits required for the operation code of an instruction depends on the total number of operation available in computer.
The operation code must consist of at least n bits for a given 2ⁿ or less distinct operations.
For example: Suppose a computer has 64 distinct operations one of them being an ADD operation.The operation code consist of 6 bit. such as 2ⁿ->2⁶=64 where n=6
So with bit configuration 110010 (operand) assign to the ADD operation.
In this case computer issues a control signal to read the bits from memory and perform addition.
At this point we must recognize the relationship between a computer operation and micro operation.

Instruction Code Format


Each computer has its own particular code format. Instruction code are specify by computer designer who design the architecture of computer.

Stored Program Organization


Organization of computer have one processor register and an instruction code format with two parts.
  1. The first part specifies the operation to be performed.
  2. Second specifies an address.
The memory address tells the control where to found operand in memory.
Above diagram show that instruction are stored in one section of memory and data in another section.Memory unit have 4096 word we need 12 bits to specify an address.
Here
2¹⁰ = 1024
2¹⁰ X 2² = 4096
2¹² = 4096
we have (2¹² X 2⁴) or 4096 X 16
So we have 16 bit memory word.
If we store each instruction code in one 16-bit memory word, we have available four bits for the opcode (operation code).
The control reads a 16-bit instruction from the portion of memory.It uses the 12-bit address of the instruction to read a 16-bit operand from the data portion of memory.

Accumulator (AC)


Computer have a single - processor register usually assign to it the name accumulator and label it (AC). The operation is performed with the memory operand and the content of AC.
If an operation is an instruction code does not need an operand from memory the rest of bit can be used for other purpose.
Example:Operations such as clear AC, complement AC and increment AC operate on data stored in the AC register. They do not an operand from memory.


Content is Reference form Compute System Architecture, MORRIS M. MANO

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Karnaugh's Map(K-MAP) | Computer Architecture

Computer Architecture ,
Karnaugh's Map(K-MAP) | Computer Architecture

Karnaugh's Map


It is used to reduce boolean algebraic equations.It is actually a truth table of another form. Let we understand more details of K-Map by the help of examples of different variables.

Two Variable K-Map


If any algebraic equation have two variable (suppose A and B) than we can say that it is two variable expression. Such as

F = A̅ B̅ + A̅ B

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Logic Gates | Computer Architecture

Computer Architecture ,
Logic Gates | Computer Architecture

Logic Gates

The manipulation of the binary information is done by logic circuit is called gates.
The input - output relationship of the binary variable for each gate can be represented in tabular form by a truth table.

Type of Logic Gates

  1. AND


    Graphical View


    Algebric Function

    X = A . B OR X = AB

    Truth Table


    A B X
    0 0 0
    0 1 0
    1 0 0
    1 1 1

  2. OR


    Graphical View


    Algebric Function

    X = A + B

    Truth Table


    A B X
    0 0 0
    0 1 1
    1 0 1
    1 1 1

  3. Inverter


    Graphical View


    Algebric Function

    X = A̅ OR X = A'

    Truth Table


    A X
    0 1
    1 0

  4. Buffer


    Graphical View


    Algebric Function

    X = A

    Truth Table


    A X
    0 0
    1 1

  5. NAND


    Graphical View


    Algebric Function

    X = (A.B)'

    Truth Table


    A B X
    0 0 1
    0 1 1
    1 0 1
    1 1 0

  6. NOR


    Graphical View


    Algebric Function

    X = (A + B)'

    Truth Table


    A B X
    0 0 1
    0 1 0
    1 0 0
    1 1 0

  7. Exclusive-OR (XOR)


    Graphical View


    Algebric Function

    X = A ⊕ B OR X = A̅.B + AB̅

    Truth Table


    A B X
    0 0 0
    0 1 1
    1 0 1
    1 1 0

  8. Exclusive-NOR


    Graphical View


    Algebric Function

    X = A ⊙ B OR X = A̅B̅ + AB

    Truth Table


    A B X
    0 0 1
    0 1 0
    1 0 0
    1 1 1

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